A common problem in application specific integrated circuits occurs when processors with different data word widths interact. For example, a 32-bit processor may interact with a 16-bit processor subsystem.
The 16-bit subsystem may include both 16 and 32 bit data words, and may also include a bridge between the wider bus of the 32-bit processor and the 16-bit processor. The data space of the 16-bit processor may contain both 16 and 32 bit wide variables. The 32 bit variables are stored in 16 bit memory as two consecutive 16 bit variables, each carrying the low and the high part of the 32 bit variable.
Typically, when the 32 bit processor wants to access the data space of the 16 bit processor to get a 16-bit variable, it would just put out the address and, depending on whether the system uses big Endian format, or little Endian format, the bridge would read from the appropriate location and return the data to the 32-bit processor.
There are several designs wherein a 32 bit processor can access the data space of the 16 bit processor to read 32 bit variables stored as two 16 bit variables. A simple form of reading the 32 bit word is having the 32 bit processor perform two 16 bit operations. However, the foregoing can have coherency issues as there can be a substantial delay between the two 16 bit operations. In the time between the two 16 bit transactions, the 16 bit processor may have changed one or both of the 16 bit words or another software thread running on the 32 bit processor may end up accessing this 16 bit pair. Thus, special Semaphore mechanism need to be employed between the processors and the threads to avoid these problems.
Processors can have, what are called byte enables. These signals correspond to the various bytes on the bus. Therefore, if the bus is 32 bits wide, there would be four byte enables. When the 32 bit processor seeks to access 32 bits, it would drive all the byte enables and the bridge could be designed to recognize that all the four bytes are required. The bridge can then perform dual 16 bit transactions in the internal data space and return the 32 bit word.
The bridge has to ensure that the 16 bit processor does not get between the two 16-bit transactions as that can possibly allow the 16 bit processor to change the value of either or both, thereby causing a faulty transaction.
The problem with this is the dependency on the availability of byte enables. Moreover, more and more systems are being designed in a manner that the dependency on byte enables is removed, because it makes the system Endian neutral.
Another way is to implement the capability to access 32 bit words is for the bridge to have a control bit that could be configured at the start of the transaction that indicates whether the next transaction with be 16 bit or a 32-bit transaction requiring the bridge to perform two 16 bit transactions.
The problem with this type of implementation is that extra effort has to be put to make the system software thread safe. Multiple processes running on the 32 bit processor may need to access the 16 bit processor data space. If one process begins a 32 bit transaction, it will have to first configure the bit to 32 bit mode, and then do a 32-bit read or write. In the meantime, if another software thread wanting to use this may also come in between the flag setting and the actual transaction, potentially corrupting the flag as the next thread may want to do a 16-bit transaction, resulting in fault operation for the other thread.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.